Prior solutions for implementing single-ended receivers were not required to operate at higher frequencies. At slower frequencies (125 MHz) the variation between rise and fall times contains more margin, and effects from simultaneous switching output (SSO) noise used up less of the relative timing budget in the receiver. At faster frequencies it becomes necessary to improve on rise- and fall-time variations and SSO noise effects. What has now become a disadvantage in prior designs is the fact that the VDDH power supply was used to power the receiver. This makes the receiver susceptible to across-supply corner cases that degrade performance to an unacceptable level. Level-shifting from the VDDH supply to the core supply produces additional jitter, and in some corner cases the level-shifting part of the circuitry may not function at all since the core voltage is now approaching levels where high-voltage Field Effect Transistor (FETs) threshold voltages are too high to operate properly.
Accordingly, a need exists for an improved singled-ended receiver.